1. Field of the Invention
The present invention relates generally to a trench DMOS power transistor and its manufacturing method and, more particularly, to a self-aligned trench DMOS transistor structure and its manufacturing methods.
2. Description of the Prior Art
A DMOS power transistor with very low on-resistance has become an important device for applications in battery protection, switching, linear regulator, amplifier and power management. Basically, the DMOS power transistor structure can be categorized into two groups: planar DMOS transistor structure and trench DMOS transistor structure. The planar DMOS transistor structure with MOS inversion channel being formed in a planar semiconductor surface, in general, exhibits a larger cell area and a larger turn-on resistance as compared to the trench DMOS transistor structure. Therefore, the trench DMOS transistor structure becomes a major trend for applications in fabricating DMOS power transistor and insulated-gate bipolar transistor (IGBT).
FIG. 1A shows a schematic cross-sectional view of a trench DMOS transistor structure of the prior art, in which a shallow trench is formed in a portion of an N− epitaxial silicon layer 125 on an N+ silicon substrate 120 by using a masking photoresist step. The shallow trench being lined with a thermal oxide layer 112 and then filled with a doped polycrystalline-silicon layer 114 as a conductive gate layer is formed to isolate p-diffusion (or p-base) regions 105. A critical masking photoresist step (not shown) is performed to selectively form n+ source diffusion rings 130. Another critical masking photoresist step (not shown) is performed to pattern an oxide layer 140 over a shallow trench region and on a portion of nearby n+ source diffusion rings 130 and, thereafter, a self-aligned ion implantation is performed to form p+ contact diffusion regions 132 for forming p-base contacts.
Apparently, the doping concentration in the p+ contact diffusion regions 132 must be smaller than that in the n+ source diffusion rings 130. A metal layer 150 is formed over a surface portion of the n+ source diffusion rings 130 and the p+ contact diffusion regions 132 and is patterned to form a source electrode. It is clearly seen that two critical masking photoresist steps are required for forming the n+ source diffusion rings 130 and the p+ diffusion regions 132 and result in difficulty in scaling down the dimension of the p-diffusion regions 105. Moreover, the parasitic resistance of the doped polycrystalline-silicon layer 114 as a gate metal layer is very large for gate interconnection of many trench DMOS transistor cells and may result in a slower switching speed.
FIG. 1B shows a schematic cross-sectional view of another trench DMOS transistor structure of the prior art, in which a large p-diffusion region 204 is formed in an N− epitaxial silicon layer 202 on an N+ silicon substrate 200 before forming the shallow trench; a gate-oxide layer 206g is lined over the shallow trench and a top portion of silicon surface; a doped polycrystalline-silicon layer 210 is formed to fill a portion of the shallow trench; and a thermal oxide layer 215 is then formed on a top portion of the doped polycrystalline-silicon layer 210. Similarly, a critical masking photoresist step (not shown) is performed to form n+ source diffusion rings 212 and another critical masking photoresist step (not shown) is performed to simultaneously pattern an oxide layer 214 and the gate-oxide layer 206g. There is no p+ diffusion region 132 as shown in FIG. 1A to improve contact resistance between the p-diffusion regions 204 and the source metal layer 216. It is clearly visualized that two critical masking photoresist steps are also required to form the n+ source diffusion rings 212 and the contacts for the source metal layer 216.
Comparing FIG. 1A and FIG. 1B, it is clearly seen that the overlapping region between the n+ source diffusion ring 212 and the doped polycrystalline-silicon layer 210 for FIG. 1B is reduced and this reduces the gate to source capacitance and improves leakage current between the n+ source diffusion rings 212 and the doped polycrystalline-silicon layer 210. Apparently, the trench DMOS transistor structure shown in FIG. 1B is also difficult to be scaled down due to two critical masking photoresist steps used to define the n+ source diffusion rings 212 and the source metal contacts.
It is therefore a major objective of the present invention to offer a self-aligned trench DMOS transistor structure being fabricated without critical masking photoresist steps.
It is another objective of the present invention to offer a self-aligned trench DMOS transistor structure with a heavily-doped source diffusion ring and a heavily-doped p-base contact diffusion region to improve device ruggedness.
It is a further objective of the present invention to offer a self-aligned trench DMOS transistor structure with different self-aligned conductive gate structures to reduce parasitic gate-interconnection resistance and capacitance.
It is yet an important objective of the present invention to offer a high-density, self-aligned trench DMOS transistor structure with a scalable p-base dimension.